A single set of these algorithms could be used to send the data to the SLCs by
juggling the states of the PSTA and SSTA inputs to the algorithm. If an SLC card’s
communication was enabled before PSTA and SSTA were switched, the newly
enabled module would send either invalid or old data to the field devices.
This is avoided by doubling the algorithms for each LC module’s hardware address
and always setting PSTA to true.
Field Devices to Controller
For data coming from the field devices to the Controller, a single set of algorithms
with both modules’ hardware addresses entered is used. By juggling the states of
PSTA and SSTA, the data is received from one or the other of the LC modules.
If, however, these states were changed when control was passed from one LC to the
other, there would be a period of time before the newly enabled LC had completed
all transactions with the field devices. During this time, old or invalid data would be
read from the LC registers.
It is possible in the Controller logic to use the ExecutedOnceReg to delay setting
one of the states after resetting the other. This has the effect of reading from neither
LC module until ExecutedOnceReg was true. Unfortunately, while neither LC
module is enabled, the algorithm sets the quality of the associated points to bad.

这些算法中的一组可用于通过以下方式将数据发送到SLC：
将PSTA和SSTA输入的状态切换到算法。如果SLC卡
在PSTA和SSTA切换之前，通信已启用，新的
启用的模块将向现场设备发送无效或旧数据。
通过将每个LC模块的硬件地址的算法加倍，可以避免这种情况
并且总是将PSTA设置为真。
现场设备至控制器
对于从现场设备到控制器的数据，一组算法
使用输入的两个模块的硬件地址。通过改变
PSTA和SSTA，从一个或另一个LC模块接收数据。
然而，当控制从一个LC传递到另一个LC时，如果这些状态发生变化
另一方面，新启用的信用证需要一段时间才能完成
与现场设备的所有交易。在此期间，旧的或无效的数据将被删除
从LC寄存器读取数据。
在控制器逻辑中，可以使用ExecuteOnCereg延迟设置
重置另一个后的一个状态。这两种方法都有阅读的效果
LC模块直到ExecuteOnCeReg为真。不幸的是
模块启用时，算法将关联点的质量设置为“坏”。