DKC03.3-200-7FW
图4-5和4-6显示了
WFTRIG信号。
图4-5：。WFTRIG输入信号定时
图4-6：。WFTRIG输出信号定时
更新*信号
任何PFI引脚都可以从外部输入更新*信号，该信号可用
作为PFI5/更新*引脚上的输出。
作为输入，在边缘检测模式下配置更新*信号。
您可以选择任何PFI引脚作为更新*的源，并配置
上升沿或下降沿的极性选择。的选定边
更新*信号更新DAC的输出。为了使用
更新*，则必须将DAC设置为发布更新模式。
作为输出，更新*信号反映实际更新脉冲，即
连接到DAC。即使更新是在外部进行的，也是如此
由另一个PFI生成。输出为激活的低脉冲和脉冲
宽度为50至75 ns。该输出在启动时设置为三态。

Figures 4-5 and 4-6 show the input and output timing requirements for the WFTRIG signal. Figure 4-5. WFTRIG Input Signal Timing Figure 4-6. WFTRIG Output Signal Timing UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, the UPDATE* signal is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of the UPDATE* signal updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode. As an output, the UPDATE* signal reflects the actual update pulse that is connected to the DACs. This is true even if the updates are being externally generated by another PFI. The output is an active low pulse with a pulse width of 50 to 75 ns. This output is set to tri-state at startup.