VMIVME-2511
提供一个可编程看门狗定时器（WDT），如果软件完整性出现故障，该定时器可用于重置系统。WDT控制状态寄存器（WCSR）WDT由WDT控制状态寄存器（WCSR）控制和监控，该寄存器位于BAR2中地址的偏移量0x08处。该寄存器中的位映射如下：“WDT超时选择”字段用于选择看门狗计时器的超时值，如下所示：“SERR/RST选择”位用于选择WDT是在本地PCI总线上生成SERR#还是系统重置。如果该位设置为“0”，WDT将生成系统复位。否则，WDT将激活本地PCI总线SERR信号。“WDT Enable”（WDT启用）位用于启用看门狗定时器功能。该位必须设置为“1”，以使看门狗定时器正常工作。请注意，由于重置后所有寄存器默认为零，因此重置后始终禁用看门狗计时器。重置后，应用软件必须重新启用看门狗计时器，以便看门狗计时器继续工作。启用看门狗计时器后，应用软件必须在选定的超时时间内刷新看门狗计时器，以防止产生重置或SERR。看门狗计时器是字段位读或写SERR/RST选择WCSR[16]R/W WDT超时选择WCSR[10..8]R/W WDT启用WCSR[0]R/W所有这些位在系统重置后默认为“0”。保留所有其他位。超时WCSR[10]WCSR[9]WCSR[8]135s 0 0 0 33.6s 0 1 2.1s 0 1 0 524ms 0 1 1 262ms 1 0 0 131ms 1 0 1 32.768ms 1 0 2.048ms 1 1 1 1 1

provide a programmable Watchdog Timer (WDT) which can be used to reset the system if software integrity fails. WDT Control Status Register (WCSR) The WDT is controlled and monitored by the WDT Control Status Register (WCSR) which is located at offset 0x08 from the address in BAR2. The mapping of the bits in this register are as follows: The “WDT Timeout Select” field is used to select the timeout value of the Watchdog Timer as follows: The “SERR/RST Select” bit is used to select whether the WDT generates an SERR# on the local PCI bus or a system reset. If this bit is set to “0”, the WDT will generate a system reset. Otherwise, the WDT will make the local PCI bus SERR# signal active. The “WDT Enable” bit is used to enable the Watchdog Timer function. This bit must be set to “1” in order for the Watchdog Timer to function. Note that since all registers default to zero after reset, the Watchdog Timer is always disabled after a reset. The Watchdog Timer must be re-enabled by the application software after reset in order for the Watchdog Timer to continue to operate. Once the Watchdog Timer is enabled, the application software must refresh the Watchdog Timer within the selected timeout period to prevent a reset or SERR# from being generated. The Watchdog Timer is Field Bits Read or Write SERR/RST Select WCSR[16] R/W WDT Timeout Select WCSR[10..8] R/W WDT Enable WCSR[0] R/W All of these bits default to “0” after system reset. All other bits are reserved. Timeout WCSR[10] WCSR[9] WCSR[8] 135s 0 0 0 33.6s 0 0 1 2.1s 0 1 0 524ms 0 1 1 262ms 1 0 0 131ms 1 0 1 32.768ms 1 1 0 2.048ms 1 1 1